Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logic function. With standard cell technology, the schematic diagram of HDL specification is synthesized into standard cells of a specific cell library.
Each cell corresponds to a logical function unit or block, which is implemented by one or more transistors that are optimized for the cell. The logic designer selects particular cells according to a number of loads attached to the cell and to an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell's transistors and cell routing data. The cell characteristics include a cell propagation delay, a model of the cell's function, input capacitance, output capacitance and output ramptime as a function of load. The propagation delay is a function of the internal delay and the output loading (or “fan-out”) of the cell.
A series of computer aided design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell, and the routed interconnections.
A timing analysis tool is then used to identify timing violations within the circuit layout. The time it takes for a signal to travel along a particular path or “net” from one sequential element to another depends on the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path, and the drive strengths of the transistors in the path.
A timing violation may be caused by a number of factors. For example, a particular cell may not have a large enough drive strength to drive the number of loads that are attached to that cell. Also, exceptionally long routing paths may cause timing violations. Timing violations can be eliminated by making adjustments at each stage in the layout process. For example, the logic diagram or HDL specification can be changed to restructure or resynthesize certain sections of logic to improve timing through that section. Additionally, other changes and adjustments may be made in the layout to improve timing considerations and/or to meet design specifications.
Once the timing violations and timing considerations have been corrected, the timing analysis tool is again utilized to identify any further timing violations within the circuit layout. The processes of timing analysis and layout adjustment may be repeated iteratively until all timing violations have been eliminated. Once the layout timing has been resolved, the netlist, the cell layout definitions, the placement data, and the routing data together form an integrated circuit layout definition, which can be utilized to fabricate an integrated circuit.
The complexity of state of the art integrated circuits may cause such iterative procedures as described above to be repeated many times in order to achieve an IC design that meets the design criteria. One technique for achieving timing recomputation is described in U.S. Pat. No. 6,553,551 and is incorporated herein by reference in its entirety.
One issue that arises in timing recomputation and resynthesis involves interconnections between pins that form a closed loop or “cycle” within a layout pattern. Computing ramptime propagation within a layout pattern that includes a cycle requires determining ramptime calculations for each pin in the cycle, which is partially determined by timing from every other pin in the cycle. If there are no cycles in the IC design, ramptime propagation calculations can be performed without any problem on a level-by-level basis. However, to utilize a conventional iterative procedure for resolving ramptime propagation issues in layout patterns with cycles, multiple calculations and iterations are required for each of the many pins of the design.
There is a need in the art for a process and method for estimating ramptime propagation in layout designs with cycles. Embodiments of the present invention provide solutions to these and other problems, and offer advantages over the prior art.